1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits and particularly to semiconductor integrated circuit devices testable and including an internal power supply potential generation circuit.
2. Description of the Background Art
In recent years there is a demand for semiconductor integrated circuit devices with larger capacities and semiconductor integrated circuit devices have accordingly been increasingly micro-fabricated. This, however, results in a semiconductor integrated circuit device having internal circuitry with a reduced breakdown voltage. Accordingly, the semiconductor integrated circuit device uses an internal power supply potential obtained by down-converting an external power supply potential. The external power supply potential is down-converted to the internal power supply potential in the semiconductor integrated circuit device by an internal power supply potential generation circuit. Thus the internal power supply potential generation circuit is also referred to as a voltage down converter (VDC).
A VDC generates an internal power supply potential which is used in a semiconductor integrated circuit device by a plurality of internal circuits. As such if the internal power supply potential drops below a predetermined potential the plurality of internal circuits cannot operate at a predetermined rate of operation.
In contrast, if the internal power supply potential exceeds a predetermined potential the plurality of internal circuits may be destroyed.
Thus the VDC is required to reduce variation of the internal power supply potential and thus supply a steady internal power supply potential.
FIG. 29 is a circuit diagram showing a configuration of a conventional VDC.
As shown in FIG. 29, a VDC500 includes a differential amplification circuit 530, a current supply transistor QD1, an internal power supply node 520, a decouple capacitor 545, and a load 550.
Differential amplification circuit 530 includes P channel MOS transistors QP1, QP2, and N channel MOS transistors QN1, QN2, QN3.
Differential amplification circuit 530 amplifies a difference in potential between an internal power supply potential int.Vdd and a reference potential Vref and outputs the amplified difference in potential to current supply transistor QD1 at the gate. In response to the output of differential amplification circuit 530, current supply transistor QD1 passes a supply current Isup from an external power supply node 510 to an internal power supply node 520. Decouple capacitor 545 reduces variation of a level in potential of the internal power supply node. Load 550 receives internal power supply potential int.Vdd from internal power supply node 520 and consumes a load current Iload.
When internal power supply potential int.Vdd drops below reference potential Vref, current supply transistor QD1 supplies internal power supply node 520 with supply current Isup. In contrast, if internal power supply potential int.Vdd exceeds reference potential Vref, current supply transistor QD1 is turned off. Thus, supply current Isup is not supplied to internal power supply node 520.
As a result, VDC500 operates to maintain internal power supply potential int.Vdd of the level of reference potential Vref.
Load current Iload consumed by load 550 will now be described.
FIG. 30 is timing plots representing an operation of VDC500 corresponding to one example of load current Iload.
FIG. 30 represents load current Iload having a current waveform observed when load 500 continuously consumes a small amount of current. Such a current waveform is observed in a dynamic random access memory (DRAM) for example at a signal buffer.
With reference to FIG. 30, when a control signal ACT has an active state the VDC is actuated. If by load current Iload internal power supply potential int.Vdd is reduced, decouple capacitor 545 operates to reduce the reduction of internal power supply potential int.Vdd. Furthermore, supply current Isup is supplied to internal power supply node 520. This prevents internal power supply potential int.Vdd from significantly dropping from reference potential Vref and thus prevents load 550 from erroneous operation.
FIG. 31 is timing plots representing an operation of VDC500 corresponding to another example of load current Iload.
FIG. 31 represents load current Iload having a current waveform observed when load 500 consumes a large amount of current. Such a current waveform is observed in a DRAM for example at a sense amplifier.
As shown in FIG. 31, when control signal ACT has an active state, the VDC is activated. When because of a large amount of load current Iload internal power supply potential int.Vdd significantly drops, supply current Isup is supplied to internal power supply node 520. There is a case, however, where supply current Isup cannot prevent the reduction of internal power supply potential int.Vdd and internal power supply potential int.Vdd thus has a large drop ΔV2. Such a reduction of internal power supply potential int.Vdd results in load 550 operating at a reduced rate.
Furthermore, decouple capacitor 545 operates to prevent the reduction of internal power supply potential int.Vdd, although to prevent the reduction of internal power supply potential int.Vdd attributed to a large amount of load current Iload, decouple capacitor 545 is required to have a capacitance accordingly increased. Increasing the capacitance of decouple capacitor 54 results in increasing the cheap area.
As a technique used to provide a steady internal power supply voltage if a large amount of load current Iload is generated, as shown in FIG. 31, a VDC including a boost circuit is used.
The boost circuit supplies current to internal power supply node 520 previously before load current Iload is generated.
The VDC including the boost circuit, however, can disadvantageously be overcharged or undercharged because of variation of external power supply potential ext.Vdd, variation of the fabrication process, and the like. Furthermore, for a semiconductor integrated circuit device having a test mode, overcharge can disadvantageously occur in conducting a test when the boost circuit operates.